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@@ -43,6 +43,7 @@ BUILT_SOURCES += tsigrecord_toWire1.wire tsigrecord_toWire2.wire
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BUILT_SOURCES += tsig_verify1.wire tsig_verify2.wire tsig_verify3.wire
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BUILT_SOURCES += tsig_verify1.wire tsig_verify2.wire tsig_verify3.wire
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BUILT_SOURCES += tsig_verify4.wire tsig_verify5.wire tsig_verify6.wire
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BUILT_SOURCES += tsig_verify4.wire tsig_verify5.wire tsig_verify6.wire
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BUILT_SOURCES += tsig_verify7.wire tsig_verify8.wire tsig_verify9.wire
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BUILT_SOURCES += tsig_verify7.wire tsig_verify8.wire tsig_verify9.wire
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+BUILT_SOURCES += tsig_verify10.wire
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# NOTE: keep this in sync with real file listing
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# NOTE: keep this in sync with real file listing
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# so is included in tarball
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# so is included in tarball
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@@ -114,6 +115,7 @@ EXTRA_DIST += tsigrecord_toWire1.spec tsigrecord_toWire2.spec
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EXTRA_DIST += tsig_verify1.spec tsig_verify2.spec tsig_verify3.spec
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EXTRA_DIST += tsig_verify1.spec tsig_verify2.spec tsig_verify3.spec
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EXTRA_DIST += tsig_verify4.spec tsig_verify5.spec tsig_verify6.spec
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EXTRA_DIST += tsig_verify4.spec tsig_verify5.spec tsig_verify6.spec
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EXTRA_DIST += tsig_verify7.spec tsig_verify8.spec tsig_verify9.spec
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EXTRA_DIST += tsig_verify7.spec tsig_verify8.spec tsig_verify9.spec
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+EXTRA_DIST += tsig_verify10.spec
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.spec.wire:
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.spec.wire:
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./gen-wiredata.py -o $@ $<
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./gen-wiredata.py -o $@ $<
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